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PDF GS8673ET18BK Data sheet ( Hoja de datos )
| Número de pieza | GS8673ET18BK | |
| Descripción | 72Mb SigmaDDR-IIIe Burst of 2 ECCRAM | |
| Fabricantes | GSI Technology | |
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GS8673ET18/36BK-675/625/550/500
260-Ball BGA
Commercial Temp
Industrial Temp
72Mb SigmaDDR-IIIe™
Burst of 2 ECCRAM™
675 MHz–500 MHz
1.35V VDD
1.2V to 1.5V VDDQ
Features
• On-Chip ECC with virtually zero SER
• Configurable Read Latency (3.0 or 2.0 cycles)
• Simultaneous Read and Write SigmaDDR-IIIe™ Interface
• Common I/O Bus
• Double Data Rate interface
• Burst of 2 Read and Write
• Pipelined read operation
• Fully coherent Read and Write pipelines
• 1.35V nominal VDD
• 1.2V JESD8-16A BIC-3 Compliant Interface
• 1.5V HSTL Interface
• ZQ pin for programmable output drive impedance
• ZT for programmable input termination impedance
• Configurable Input Termination
• IEEE 1149.1 JTAG-compliant Boundary Scan
• 260-ball, 14 mm x 22 mm, 1 mm ball pitch BGA package
–K: 5/6 RoHS-compliant package
–GK: 6/6 RoHS-compliant package
SigmaDDR-IIIe™ Family Overview
SigmaDDR-IIIe ECCRAMs are the Common I/O half of the
SigmaQuad-IIIe/SigmaDDR-IIIe family of high performance
ECCRAMs. Although very similar to GSI's second generation
of networking SRAMs (the SigmaQuad-II/SigmaDDR-II
family), these third generation devices offer several new
features that help enable significantly higher performance.
Clocking and Addressing Schemes
The GS8673ET18/36BK SigmaDDR-IIIe ECCRAMs are
synchronous devices. They employ dual, single-ended master
clocks, CK and CK. These clocks are single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. CK and CK are used to control the address and control
input registers, as well as all output timing.
The KD and KD clocks are dual mesochronous (with respect to
CK and CK) input clocks that are used to control the data input
registers. Consequently, data input setup and hold windows
can be optimized independently of address and control input
setup and hold windows.
Each internal read and write operation in a SigmaDDR-IIIe B2
ECCRAM is two times wider than the device I/O bus. An input
data bus de-multiplexer is used to accumulate incoming data
before it is simultaneously written to the memory array. An
output data multiplexer is used to capture the data produced
from a single memory array read and then route it to the
appropriate output drivers as needed. Therefore, the address
field of a SigmaDDR-IIIe B2 ECCRAM is always one address
pin less than the advertised index depth (e.g. the 4M x 18 has
2M addressable index).
On-Chip Error Correction Code
GSI's ECCRAMs implement an ECC algorithm that detects
and corrects all single-bit memory errors, including those
induced by Soft Error Rate (SER) events such as cosmic rays,
alpha particles, etc. The resulting SER of these devices is
anticipated to be <0.002 FITs/Mb — a 5-order-of-magnitude
improvement over comparable SRAMs with no On-Chip ECC,
which typically have an SER of 200 FITs/Mb or more. SER
quoted above is based on reading taken at sea level.
Speed Bin
-675
-625
-550
-500
Parameter Synopsis
Operating Frequency
675 / 450 MHz
625 / 400 MHz
550 / 375 MHz
500 / 333 MHz
Data Rate (per pin)
1350 / 900 Mbps
1250 / 800 Mbps
1100 / 750 Mbps
1000 / 666 Mbps
Read Latency
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
3.0 / 2.0
VDD
1.3V to 1.4V
1.3V to 1.4V
1.25V to 1.4V
1.25V to 1.4V
Rev: 1.06 5/2012
1/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
1 page  
GS8673ET18/36BK-675/625/550/500
Pin Description (Continued)
Symbol
Description
MZT[1:0]
Input Termination Mode Select—Selects the termination mode used for all terminated inputs. Must be tied
High or Low.
MZT[1:0] = 00: disabled.
MZT[1:0] = 01: RT/2 Thevenin-equivalent (pull-up = RT, pull-down = RT).
MZT[1:0] = 10: RT Thevenin-equivalent (pull-up = 2*RT, pull-down = 2*RT).
MZT[1:0] = 11: reserved.
PZT[1:0]
Input Termination Configuration Select—Selects which inputs are terminated. Must be tied High or Low.
PZT[1:0] = 00: Write Data only.
PZT[1:0] = 01: Write Data, Input Clocks.
PZT[1:0] = 10: Write Data, Address, Control.
PZT[1:0] = 11: Write Data, Address, Control, Input Clocks.
MVQ
VDD
VDDQ
VREF
VSS
TCK
I/O Voltage Select—Indicates what voltage is supplied to the VDDQ pins. Must be tied High or Low.
MVQ = 0: Configure for 1.2V to 1.35V nominal VDDQ.
MVQ = 1: Configure for 1.5V nominal VDDQ.
Core Power Supply—1.35V nominal core supply voltage.
I/O Power Supply—1.2V to 1.5V nominal I/O supply voltage. Configured via MVQ pin.
Input Reference Voltage—Input buffer reference voltage.
Ground
JTAG Clock
TMS JTAG Mode Select—Weakly pulled High internally.
TDI JTAG Data Input—Weakly pulled High internally.
TDO JTAG Data Output
MCH Must Connect High—May be tied to VDDQ directly or via a 1kΩ resistor.
MCL Must Connect Low—May be tied to VSS directly or via a 1kΩ resistor.
NC
No Connect—There is no internal chip connection to these pins. They may be left unconnected, or tied High
or Low.
Not Used, Input—There is an internal chip connection to these input pins, but they are unused by the
NUI device. They are pulled Low internally. They may be left unconnected or tied Low. They should not be tied
High.
Not Used Input/Output—There is an internal chip connection to these I/O pins, but they are unused by the
NUIO device. The drivers are tri-stated internally. They are pulled Low internally. They may be left unconnected or
tied Low. They should not be tied High.
Type
Input
Input
Input
—
—
—
—
Input
Input
Input
Output
Input
Input
—
Input
I/O
Rev: 1.06 5/2012
5/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
5 Page 
GS8673ET18/36BK-675/625/550/500
Extended DQ Truth Table - RL = 2
LD R/W
Current Operation
↑CK ↑CK
(tn) (tn)
10
00
11
01
(tn)
NOPw
Write
NOPr
Read
DQ State
↑CK
(tn+2)
Termination Enabled
Termination Enabled
Termination Disabled, Drive Low
Termination Disabled, Drive Read Data
Extended DQ Truth Table - RL = 3
LD R/W
Current Operation
DQ State
↑CK ↑CK
(tn) (tn)
(tn)
↑CK
(tn+2)
↑CK
(tn+3)
10
NOPw
Termination Enabled
---
00
Write
Termination Enabled
---
11
NOPr
Termination Disabled, Drive Low
---
01
Read
Termination Disabled, Drive Low
Drive Read Data
Note:
When a Read operation is initiated in cycle “n”, R/W must be “High” at ↑CK of cycle “n+1” (i.e. a Read operation must always be followed by a
Read or NOPr operation). In that case, the DQ state in cycle “n+3” is “Drive Read Data”, as indicated above.
NOPr/NOPw Requirements vs. Read Latency
When DQ input termination is enabled, the number of NOPw + NOPr needed during Write-to-Read transitions, and the number of
NOPr + NOPw needed during Read-to-Write transitions, vary with Read Latency, as follows:
Read Latency
Write-to-Read Transition
Read-to-Write
0 NOPw + 2 NOPr
2 NOPr + 3 NOPw
2
(0 NOPw after Write is the minimum requirement)
(1 NOPr after Read is the minimum requirement)
(1 NOPr before Read is the minimum requirement)
(2 NOPw before Write is the minimum requirement)
0 NOPw + 1 NOPr
3 NOPr + 3 NOPw
3
(0 NOPw after Write is the minimum requirement)
(2 NOPr after Read is the minimum requirement)
(0 NOPr before Read is the minimum requirement)
(2 NOPw before Write is the minimum requirement)
Note:
The non-parenthetical information listed in the table above depicts the NOPr / NOPw requirements during Write-to-Read and Read-to-Write
transitions that should be sufficient, in most applications, to ensure that the DQ bus is never pulled to VDDQ/2. They are not, however, absolute
requirements. In some applications fewer NOPr / NOPw may be sufficient, and in other applications more NOPr / NOPw may be required.
DQ State Transition Timing Specifications
Parameter
CK Clock High to DQ State Transition
Symbol
tKHDQT
Min
–0.4
Max Units
0.4 ns
Rev: 1.06 5/2012
11/34
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2011, GSI Technology
11 Page | ||
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