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What is GS8182T18BD?

This electronic component, produced by the manufacturer "GSI Technology", performs the same function as "18Mb SigmaDDR-II Burst of 2 SRAM".


GS8182T18BD Datasheet PDF - GSI Technology

Part Number GS8182T18BD
Description 18Mb SigmaDDR-II Burst of 2 SRAM
Manufacturers GSI Technology 
Logo GSI Technology Logo 


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GS8182T08/09/18/36BD-400/375/333/300/250/200/167
165-Bump BGA
Commercial Temp
Industrial Temp
18Mb SigmaDDR-II™
Burst of 2 SRAM
400 MHz–167 MHz
1.8 V VDD
1.8 V and 1.5 V I/O
Features
• Simultaneous Read and Write SigmaDDR-II™ Interface
• Common I/O bus
• JEDEC-standard pinout and package
• Double Data Rate interface
• Byte Write (x36 and x18) and Nybble Write (x8) function
• Burst of 2 Read and Write
• 1.8 V +100/–100 mV core power supply
• 1.5 V or 1.8 V HSTL Interface
• Pipelined read operation with self-timed Late Write
• Fully coherent read and write pipelines
• ZQ pin for programmable output drive strength
• IEEE 1149.1 JTAG-compliant Boundary Scan
• Pin-compatible with present 9Mb, 36Mb, and 72Mb and
future 144Mb devices
• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package
• RoHS-compliant 165-bump BGA package available
SigmaDDR-IIFamily Overview
The GS8182T08/09/18/36BD are built in compliance with the
SigmaDDR-II SRAM pinout standard for Common I/O
synchronous SRAMs. They are 18,874,368-bit (18Mb)
SRAMs. The GS8182T08/09/18/36BD SigmaDDR-II SRAMs
are just one element in a family of low power, low voltage
HSTL I/O SRAMs designed to operate at the speeds needed to
implement economical high performance networking systems.
Clocking and Addressing Schemes
The GS8182T08/09/18/36BD SigmaDDR-II SRAMs are
synchronous devices. They employ two input register clock
inputs, K and K. K and K are independent single-ended clock
inputs, not differential inputs to a single differential clock input
buffer. The device also allows the user to manipulate the
output register clock inputs quasi independently with the C and
C clock inputs. C and C are also independent single-ended
clock inputs, not differential inputs. If the C clocks are tied
high, the K clocks are routed internally to fire the output
registers instead.
Each internal read and write operation in a SigmaDDR-II B2
RAM is two times wider than the device I/O bus. An input data
bus de-multiplexer is used to accumulate incoming data before
it is simultaneously written to the memory array. An output
data multiplexer is used to capture the data produced from a
single memory array read and then route it to the appropriate
output drivers as needed.
When a new address is loaded into a x18 or x36 version of the
part, A0 is used to initialize the pointers that control the data
multiplexer / de-multiplexer so the RAM can perform "critical
word first" operations. From an external address point of view,
regardless of the starting point, the data transfers always follow
the same sequence {0, 1} or {1, 0} (where the digits shown
represent A0).
Unlike the x18 and x36 versions, the input and output data
multiplexers of the x8 and x9 versions are not preset by
address inputs and therefore do not allow "critical word first"
operations. The address fields of the x8 and x9 SigmaDDR-II
B2 RAMs are one address pin less than the advertised index
depth (e.g., the 2M x 8 has a 1M addressable index, and A0 is
not an accessible address pin).
Parameter Synopsis
tKHKH
tKHQV
-400
2.5 ns
0.45 ns
-375
2.67 ns
0.45 ns
-333
3.0 ns
0.45 ns
-300
3.3 ns
0.45 ns
-250
4.0 ns
0.45 ns
-200
5.0 ns
0.45 ns
-167
6.0 ns
0.5 ns
Rev: 1.04c 11/2011
1/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology

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GS8182T18BD equivalent
GS8182T08/09/18/36BD-400/375/333/300/250/200/167
2M x 8 SigmaDDR-II SRAM—Top View
1 2 3 4 5 6 7 8 9 10 11
A
CQ
NC/SA
(72Mb)
SA
R/W NW1
K
NC/SA
(144Mb)
LD
SA
NC/SA
(36Mb)
CQ
B
NC
NC
NC
SA
NC/SA
(288Mb)
K
NW0 SA
NC
NC DQ3
C NC NC NC VSS SA SA SA VSS NC NC NC
D NC NC NC VSS VSS VSS VSS VSS NC NC NC
E NC NC DQ4 VDDQ VSS VSS VSS VDDQ NC NC DQ2
F
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
NC
NC
G NC NC DQ5 VDDQ VDD VSS VDD VDDQ NC NC NC
H
Doff
VREF
VDDQ
VDDQ
VDD
VSS
VDD
VDDQ
VDDQ
VREF
ZQ
J
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
DQ1
NC
K
NC
NC
NC
VDDQ
VDD
VSS
VDD VDDQ NC
NC
NC
L
NC
DQ6
NC
VDDQ
VSS
VSS
VSS VDDQ NC
NC DQ0
M NC NC NC VSS VSS VSS VSS VSS NC NC NC
N NC NC NC VSS SA SA SA VSS NC NC NC
P NC NC DQ7 SA SA C SA SA NC NC NC
R
TDO TCK
SA
SA
SA
C
SA SA SA TMS TDI
11 x 15 Bump BGA—13 x 15 mm2 Body—1 mm Bump Pitch
Notes:
1. Unlike the x36 and x18 versions of this device, the x8 and x9 versions do not give the user access to A0. SA0 is set to 0 at the beginning
of each access.
2. NW0 controls writes to DQ0:DQ3; NW1 controls writes to DQ4:DQ7.
Rev: 1.04c 11/2011
5/36
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2007, GSI Technology


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