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What is UT8SP2M48?

This electronic component, produced by the manufacturer "Aeroflex Circuit Technology", performs the same function as "96Megabit Pipelined SSRAM".


UT8SP2M48 Datasheet PDF - Aeroflex Circuit Technology

Part Number UT8SP2M48
Description 96Megabit Pipelined SSRAM
Manufacturers Aeroflex Circuit Technology 
Logo Aeroflex Circuit Technology Logo 


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Standard Products
UT8SP2M48 96Megabit Pipelined SSRAM
Preliminary Datasheet
www.aeroflex.com/memories
April 2015
FEATURES
Synchronous SRAM organized as 2Meg words x 48bit
Continuous Data Transfer (CDT) architecture eliminates
wait states between read and write operations
Supports 40MHz to 133MHz bus operations
Internally self-timed output buffer control eliminates the
need for synchronous output enable
Registered inputs and outputs for pipelined operation
Single 2.5V to 3.3V supply
Clock-to-output time
- Clk to Q = 7ns
Clock Enable (CEN) pin to enable clock and suspend
operation
Synchronous self-timed writes
Three Chip Enables (CS0, CS1, CS2) for simple depth
expansion
"ZZ" Sleep Mode option for partial power-down
"SHUTDOWN" Mode option for deep power-down
Four Word Burst Capability--linear or interleaved
Operational Environment
- Total Dose: 100 krad(Si)
- SEL Immune: 100MeV-cm2/mg
- SEU error rate: 1.7x10-6 errors/bit-day
Package options:
- 288-lead CLGA, CCGA, and CBGA
Standard Microelectronics Drawing (SMD) 5962-15213
- QMLQ and Q+ pending
INTRODUCTION
The UT8SP2M48 is a high performance 100,663,296-bit
synchronous static random access memory (SSRAM) device
that is organized as 2M words of 48 bits. This device is
equipped with three chip selects (CS0, CS1, and CS2), a write
enable (WE), and an output enable (OE) pin, allowing for
significant design flexibility without bus contention. The
device supports a four word burst function using (ADV_LD).
All synchronous inputs are registered on the rising edge of the
clock provided the Clock Enable (CEN) input is enabled LOW.
Operations are suspended when CEN is disabled HIGH and the
previous operation is extended. Write operation control signals
are WE and six byte write enables BWE[5:0]. All write
operations are performed by internal self-timed circuitry.
For easy bank selection, three synchronous Chip Enables
(CS0, CS1, CS2) and an asynchronous Output Enable (OE)
provide for output tri-state control. The output drivers are
synchronously tri-stated during the data portion of a write
sequence to avoid bus contention.
36-00-01-001
Ver. 1.1.0
1 Aeroflex Microelectronics Solutions - HiRel

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UT8SP2M48 equivalent
DEVICE OPERATION
The UT8SP2M48 is synchronous-pipelined SSRAM designed
specifically to eliminate wait states during Write/Read or Read/
Write transitions. All synchronous inputs and outputs are
registered on the rising edge of clock. The clock signal is enabled
by the Clock Enable input (CEN). When CEN is HIGH, the clock
signal is disregarded and all internal states are maintained. All
synchronous operations are qualified by CEN. Once power-up
requirements have been satisfied, the input clock may only be
stopped during sleep (ZZ is HIGH) or shutdown mode
(SHUTDOWN is HIGH). Maximum access delay from the
rising edge of clock (tCQV) is 7ns (133 MHz device).
Access is initiated by asserting all three Chip Enables
(CS0, CS1, CS2) active at the rising edge of the clock with
Clock Enable (CEN) and ADV_LD asserted LOW. The
address presented to the device will be registered. Access can
be either a Read or Write operation, depending on the status of
the Write Enable (WE).
Write operations are initiated by the Write Enable (WE) input.
All write commands are controlled by built in synchronous
self-timed circuitry.
Three synchronous Chip Enables (CS0, CS1, CS2) and an
asynchronous Output Enable (OE) simplify memory depth
expansion. All operations (Reads, Writes, and Deselects) are
pipelined. ADV_LD must be driven LOW once the device has
been deselected in order to load a new address and command
for the next operation.
Single Read Accesses
A read access is initiated when the following device inputs are
present at rising clock edge: CEN is enabled LOW, CS0, CS1,
and CS2 are all enabled, the Write Enable input signal WE is
disabled HIGH and ADV_LD is asserted LOW. The addresses
present at the address inputs A[20:0] are registered and
presented to the memory. Data propagates to the input of the
output register. Data will be available to the bus 7ns after the
next rising clock edge provided OE is enabled LOW. After the
first clock of the read access, the output buffers are controlled
by OE and the internal control logic. OE must be enabled
LOW to drive requested data. During the next rising clock, any
operation (Read/Write/Deselect) may be initiated. Device
deselection is also pipelined. If any of the chip enables are
false at rising edge of clock, the device outputs will tri-state
after the following rising clock edge.
Burst Read Accesses
The UT8SP2M48 has an internal burst counter allowing up to
four reads to be performed from a single address input. A new
address can only be loaded when ADV_LD is driven LOW.
New addresses are loaded into the SSRAM, as described by
the Single Read Access section. The burst counter operates in
either linear or interleave and is controlled by the MODE input
at power up. When MODE pin is LOW, the burst sequence is
linear. The burst sequence is interleaved when MODE is
HIGH. A0 and A1 are controlled by the burst counter. The
burst counter will wrap around when needed. The burst
counter increments anytime ADV_LD is HIGH and CEN is
low. The operation selected by the state of WE is latched at the
beginning of the sequence and maintained throughout.
Single Write Accesses
A write access is initiated when the following device inputs are
present at rising clock edge: CEN is enabled LOW, CS0, CS1,
and CS2 are all enabled, the Write Enable input signal WE is
enabled LOW and ADV_LD is asserted LOW. The addresses
present at the address inputs A[20:0] are registered and
presented to the memory core. Data I/Os are tri-stated at the
next rising edge of clock regardless of state of OE. The write is
completed after the next rising clock edge using data present
on DQ pins. Each byte of data is individually qualified by its
applicable byte write enable input (see Table 2). When the
input low, the applicable DQ inputs are registered to memory.
When the input is high, the applicable DQ pins are ignored.
To avoid bus contention data should not be driven to DQs
when outputs are active. The Output Enable (OE) may be
disabled HIGH before applying data to the DQ lines. This will
tri-state the DQ output drivers. As an additional feature DQ
lines are automatically tri-stated during the data portion of a
Write cycle, regardless of the state of OE.
Burst Write Accesses
The UT8SP2M48 has an internal burst counter allowing up to
four writes to be performed from a single address input. A new
address can only be loaded when ADV_LD is driven LOW.
New addresses are loaded into the SSRAM, as described in the
Single Write Access section. When ADV_LD is driven HIGH
on the subsequent clock rise, where CEN is LOW, the Chip
Enables (CS0, CS1, CS2) and WE inputs are ignored and the
burst counter is incremented. The BWE[5:0] inputs must be
LOW in each cycle of the burst write in order to qualify each
respective byte of data.
36-00-01-001
Ver. 1.1.0
5 Aeroflex Microelectronics Solutions - HiRel


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