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PDF UT8SF2M32 Data sheet ( Hoja de datos )
| Número de pieza | UT8SF2M32 | |
| Descripción | 64Megabit Flow-thru SSRAM | |
| Fabricantes | Aeroflex Circuit Technology | |
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Standard Products
UT8SF2M32 64Megabit Flow-thru SSRAM
Preliminary Datasheet
www.aeroflex.com/memories
April 2015
FEATURES
Synchronous SRAM organized as 2Meg words x 32bit
Continuous Data Transfer (CDT) architecture eliminates
wait states between read and write operations
Supports 40MHz to 80MHz bus operations
Internally self-timed output buffer control eliminates the
need for synchronous output enable
Registered inputs for flow-thru operations
Single 2.5V to 3.3V supply
Clock-to-output times
- Clk to Q = 12ns
Clock Enable (CEN) pin to enable clock and suspend
operation
Synchronous self-timed writes
Three Chip Enables (CS0, CS1, CS2) for simple depth
expansion
"ZZ" Sleep Mode option for partial power-down
"SHUTDOWN" Mode option for deep power-down
Four Word Burst Capability--linear or interleaved
Operational Environment
- Total Dose: 100 krad(Si)
- SEL Immune: ≤ 100MeV-cm2/mg
- SEU error rate: 1 x 10 -15errors/bit-day
with internal error correction
Package options:
- 288-lead CLGA, CCGA, and CBGA
Standard Microelectronics Drawing (SMD) 5962-15214
- QMLQ and Q+ pending
INTRODUCTION
The UT8SF2M32 is a high performance 67,108,864-bit
synchronous static random access memory (SSRAM) device
that is organized as 2M words of 32 bits. This device is
equipped with three chip selects (CS0, CS1, and CS2), a write
enable (WE), and an output enable (OE) pin, allowing for
significant design flexibility without bus contention. The
device supports a four word burst function using (ADV_LD).
The device achieves a very low error rate by employing
SECDED (single error correction double error detection)
EDAC (error detection and correction) scheme during read/
write operations as well as additional autonomous data
scrubbing. The data scrubbing is performed in the background
and is invisible to the user.
All synchronous inputs are registered on the rising edge of the
clock provided the Clock Enable (CEN) input is enabled LOW.
Operations are suspended when CEN is disabled HIGH and the
previous operation is extended. Write operation control signals
are WE and FLSH_PIPE. All write operations are performed
by internal self-timed circuitry.
For easy bank selection, three synchronous Chip Enables
(CS0, CS1, CS2) and an asynchronous Output Enable (OE)
provide for output tri-state control. The output drivers are
synchronously tri-stated during the data portion of a write
sequence to avoid bus contention.
36-00-01-006
Ver. 1.9.4
1 Aeroflex Microelectronics Solutions - HiRel
1 page  
NUIL
NUIH
NC
TDO4
TDI4
TMS4
TCK4
Not used Input Low: Pins designated as NUIL need to be externally
connected by user to VSS Q through a >10kΩ±10% resistor.
Not used Input High: Pins designated as NUIH need to be externally
connected by user to VDDQ through a >10kΩ±10% resistor.
No Connects. Not internally connected to the die.
JTAG circuit serial data output. Package pin requires a pull-up through
>10kΩ±10% resistor to VDDQ.
JTAG circuit serial data input. Device pin internally connected through a
75kΩ±10% resistor to VDDQ.
JTAG controller Test Mode Select. Device pin internally connected through
a 75kΩ±10% resistor to VDDQ.
JTAG circuit Clock input. Package pin requires a pull-up through
>10kΩ±10% resistor to VDDQ.
--
--
---
JTAG Serial Output
Synchronous
JTAG Serial Input
Synchronous
Test Mode Select
Synchronous
JTAG Clock
Note:
1. DQ[51:32] are ignore during write and tri-stated during read activities unless EDACEN is deselected. (See Read Access Error Correction and Detection page 6.)
2. Reference application note AN-MEM-004 for additional READY signal information.
3. DC inputs are established at power up and cannot be switched while power is applied to the device.
4. Reference application note AN-MEM-05 for JTAG operations. JTAG operations are intended for terrestrial use and not guaranteed in radiation environment.
36-00-01-006
Ver. 1.9.4
5 Aeroflex Microelectronics Solutions - HiRel
5 Page 
ABSOLUTE MAXIMUM RATINGS1
(Referenced to VSS)
SYMBOL
VDD/VDDQ
VIN
IIO
PD
TJ
ΘJC
TSTG
Supply Voltage2
PARAMETER
Voltage on any pin2
DC I/O current per pin @ TJ = 135o for 15 years
Package power dissipation permitted @ TC = 105°C3
Maximum junction temperature
Thermal resistance junction to case
Storage temperature
VALUE
-0.5 to 4.0
-0.3 to VDDQ+0.3
+10
15
+150
3
-65 to +150
UNIT
V
V
mA
W
oC
oC/W
oC
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions.
2. All voltages are referenced to VSS.
3. Per MIL-STD-883, Method 1012, Section 3.4.1 PD = (TJ(max) - TC(max))
ΘJC
OPERATIONAL ENVIRONMENTS1
PARAMETER
Total Ionizing Dose (TID)
Heavy Ion Error Rate
Single Event Latchup (SEL) immune2
LIMIT
100K
1x10-15
≤ 100
Notes:
1. Adams 90% worst case environment, Geosynchronous orbit, 100mils of aluminum
2. Temperature = 105oC; VDD and VDDQ = 3.6V
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VDD
VDDQ
TC
VIN
TJ
Core supply voltage
I/O power supply voltage
Case temperature range
DC input voltage
Junction Temperature
UNITS
rad(Si)
Errors/Bit-Day
MeV-cm2/mg
LIMITS
2.3V to VDDQ
2.3V to 3.6V
-55°C to +105°C
0V to VDDQ
-55°C to +125°C
36-00-01-006
Ver. 1.9.4
11 Aeroflex Microelectronics Solutions - HiRel
11 Page | ||
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