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PDF UT54ACS54 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACS54 | |
| Descripción | 4-Wide AND-OR-INVERT Gates | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT54ACS54/UT54ACTS54
4-Wide AND-OR-INVERT Gates
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS54 - SMD 5962-96532
UT54ACTS54 - SMD 5962-96533
DESCRIPTION
The UT54ACS54 and the UT54ACTS54 are 4-wide AND-OR-
INVERT gates. The devices perform the Boolean function:
Y = AB+CD+EF+GH
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
INPUT
OUTPUT
ABCDE FGH
Y
HHXXXXXX
L
XXHHXXXX
L
XXXXHHXX
L
XXXXXXHH
L
LXLXLXLX
H
XLXLXLXL
H
LOGIC SYMBOL
A (1)
B (13)
C (2)
(3)
D
(4)
E
F (5)
(9)
G
(10)
H
&
&
&
&
>1
(8)
Y
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and
IEC Publication 617-12.
PINOUTS
14-Pin DIP
Top View
A 1 14 VDD
C 2 13 B
D 3 12 NC
E 4 11 NC
F 5 10 H
NC 6
9G
VSS 7
8Y
14-Lead Flatpack
Top View
A 1 14
C 2 13
D 3 12
E 4 11
F 5 10
NC 6 9
VSS 7 8
LOGIC DIAGRAM
A
B
C
D
E
F
G
H
1
VDD
B
NC
NC
H
G
Y
Y
1 page  
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPHL From any input to Y output
tPLH From any input to Y output
1 16 ns
1 13 ns
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
5
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet UT54ACS54.PDF ] | |
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