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PDF 74LVC2G86-Q100 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2G86-Q100 | |
| Descripción | Dual 2-input EXCLUSIVE-OR gate | |
| Fabricantes | NXP Semiconductors | |
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74LVC2G86-Q100
Dual 2-input EXCLUSIVE-OR gate
Rev. 1 — 7 May 2013
Product data sheet
1. General description
The 74LVC2G86-Q100 provides a dual 2-input EXCLUSIVE-OR gate.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from 40 C to +85 C and from 40 C to +125 C
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant inputs for interfacing with 5 V logic
High noise immunity
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8B/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0 )
24 mA output drive (VCC = 3.0 V)
CMOS low-power consumption
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
Multiple package options
1 page  
NXP Semiconductors
74LVC2G86-Q100
Dual 2-input EXCLUSIVE-OR gate
10. Static characteristics
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ[1]
Tamb = 40 C to +85 C
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V
0.65 VCC -
VCC = 2.3 V to 2.7 V
1.7 -
VCC = 2.7 V to 3.6 V
VCC = 4.5 V to 5.5 V
2.0 -
0.7 VCC -
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V
--
VCC = 2.3 V to 2.7 V
VCC = 2.7 V to 3.6 V
--
--
VCC = 4.5 V to 5.5 V
--
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
-
-
IO = 4 mA; VCC = 1.65 V
- 0.07
IO = 8 mA; VCC = 2.3 V
- 0.12
IO = 12 mA; VCC = 2.7 V
- 0.17
IO = 24 mA; VCC = 3.0 V
- 0.33
IO = 32 mA; VCC = 4.5 V
- 0.39
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V
VCC 0.1
1.2
1.9
2.2
2.3
3.8
-
-
-
1.54
2.15
2.50
2.62
4.11
0.1
0.1
ICC
ICC
supply current
additional supply current
VI = 5.5 V or GND;
VCC = 1.65 V to 5.5 V; IO = 0 A
per pin; VI = VCC 0.6 V; IO = 0 A;
VCC = 2.3 V to 5.5 V
- 0.1
-5
CI input capacitance
- 2.5
Max Unit
-V
-V
-V
-V
0.35 VCC V
0.7 V
0.8 V
0.3 VCC V
0.1 V
0.45 V
0.3 V
0.4 V
0.55 V
0.55 V
-V
-V
-V
-V
-V
-V
5 A
10 A
10 A
500 A
- pF
74LVC2G86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 May 2013
© NXP B.V. 2013. All rights reserved.
5 of 14
5 Page 
NXP Semiconductors
14. Abbreviations
Table 11. Abbreviations
Acronym
Description
CMOS
Complementary Metal-Oxide Semiconductor
DUT
Device Under Test
ESD
ElectroStatic Discharge
HBM
Human Body Model
MIL Military
MM Machine Model
TTL Transistor-Transistor Logic
15. Revision history
Table 12. Revision history
Document ID
Release date
74LVC2G86_Q100 v.1 20130507
Data sheet status
Product data sheet
74LVC2G86-Q100
Dual 2-input EXCLUSIVE-OR gate
Change notice
-
Supersedes
-
74LVC2G86_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 7 May 2013
© NXP B.V. 2013. All rights reserved.
11 of 14
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