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PDF 74LVC2G00 Data sheet ( Hoja de datos )
| Número de pieza | 74LVC2G00 | |
| Descripción | Dual 2-input NAND gate | |
| Fabricantes | NXP Semiconductors | |
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74LVC2G00
Dual 2-input NAND gate
Rev. 12 — 8 April 2013
Product data sheet
1. General description
The 74LVC2G00 provides a 2-input NAND gate function.
Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these
devices as translators in a mixed 3.3 V and 5 V environment.
This device is fully specified for partial power-down applications using IOFF. The IOFF
circuitry disables the output, preventing the damaging backflow current through the device
when it is powered down.
2. Features and benefits
Wide supply voltage range from 1.65 V to 5.5 V
5 V tolerant outputs for interfacing with 5 V logic
High noise immunity
24 mA output drive (VCC = 3.0 V)
CMOS low power consumption
Complies with JEDEC standard:
JESD8-7 (1.65 V to 1.95 V)
JESD8-5 (2.3 V to 2.7 V)
JESD8-B/JESD36 (2.7 V to 3.6 V)
Latch-up performance exceeds 250 mA
Direct interface with TTL levels
Inputs accept voltages up to 5 V
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
1 page  
NXP Semiconductors
74LVC2G00
Dual 2-input NAND gate
9. Recommended operating conditions
Table 6.
Symbol
VCC
VI
VO
Operating conditions
Parameter
supply voltage
input voltage
output voltage
Tamb
t/V
ambient temperature
input transition rise and fall rate
10. Static characteristics
Conditions
Active mode
Power-down mode
VCC = 1.65 V to 2.7 V
VCC = 2.7 V to 5.5 V
Min Max Unit
1.65 5.5
V
0 5.5 V
0
VCC
V
0 5.5 V
40
+125
C
- 20 ns/V
- 10 ns/V
Table 7. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter
Conditions
Min Typ
Tamb = 40 C to +85 C[1]
VIH HIGH-level input voltage VCC = 1.65 V to 1.95 V
0.65 VCC -
VCC = 2.3 V to 2.7 V
1.7 -
VCC = 2.7 V to 3.6 V
2.0 -
VCC = 4.5 V to 5.5 V
0.7 VCC -
VIL LOW-level input voltage VCC = 1.65 V to 1.95 V
--
VCC = 2.3 V to 2.7 V
--
VCC = 2.7 V to 3.6 V
--
VCC = 4.5 V to 5.5 V
--
VOH HIGH-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
IO = 8 mA; VCC = 2.3 V
IO = 12 mA; VCC = 2.7 V
IO = 24 mA; VCC = 3.0 V
IO = 32 mA; VCC = 4.5 V
VCC 0.1
1.2
1.9
2.2
2.3
3.8
-
1.53
2.13
2.50
2.60
4.10
VOL LOW-level output voltage VI = VIH or VIL
IO = 100 A; VCC = 1.65 V to 5.5 V
IO = 4 mA; VCC = 1.65 V
-
-
-
0.08
IO = 8 mA; VCC = 2.3 V
- 0.14
IO = 12 mA; VCC = 2.7 V
- 0.19
IO = 24 mA; VCC = 3.0 V
- 0.37
IO = 32 mA; VCC = 4.5 V
II
input leakage current
VI = 5.5 V or GND; VCC = 0 V to 5.5 V
IOFF power-off leakage current VI or VO = 5.5 V; VCC = 0 V
-
-
-
0.43
0.1
0.1
Max Unit
-V
-V
-V
-V
0.35 VCC V
0.7 V
0.8 V
0.3 VCC V
-V
-V
-V
-V
-V
-V
0.1 V
0.45 V
0.3 V
0.4 V
0.55 V
0.55 V
5 A
10 A
74LVC2G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
5 of 20
5 Page 
NXP Semiconductors
74LVC2G00
Dual 2-input NAND gate
XSON8: plastic extremely thin small outline package; no leads; 8 terminals; body 1 x 1.95 x 0.5 mm
b
1234
4×
L1 L (2)
e
8
e1
7
e1
6
e1
5
8× A
(2)
A1
D
SOT833-1
E
terminal 1
index area
01
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max
A1
max
b
D
E
e
mm
0.5
0.04
0.25
0.17
2.0
1.9
1.05
0.95
0.6
scale
e1 L L1
0.5
0.35 0.40
0.27 0.32
Notes
1. Including plating thickness.
2. Can be visible in some manufacturing processes.
OUTLINE
VERSION
IEC
REFERENCES
JEDEC
JEITA
SOT833-1
---
MO-252
---
2 mm
EUROPEAN
PROJECTION
ISSUE DATE
07-11-14
07-12-07
Fig 12. Package outline SOT833-1 (XSON8)
74LVC2G00
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 12 — 8 April 2013
© NXP B.V. 2013. All rights reserved.
11 of 20
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| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet 74LVC2G00.PDF ] | |
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