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PDF ST72212G2 Data sheet ( Hoja de datos )
| Número de pieza | ST72212G2 | |
| Descripción | 8-BIT MCU | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ST72212G2 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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ST72101/ST72212/ST72213
8-BIT MCU WITH 4 TO 8K ROM/OTP/EPROM,
256 BYTES RAM, ADC, WDG, SPI AND 1 OR 2 TIMERS
DATASHEET
s User Program Memory (ROM/OTP/EPROM):
4 to 8K bytes
s Data RAM: 256 bytes, including 64 bytes of
stack
s Master Reset and Power-On Reset
t(s)s Run, Wait, Slow, Halt and RAM Retention
modes
cs 22 multifunctional bidirectional I/O lines:
du– 22 programmable interrupt inputs
ro )– 8 high sink outputs
P t(s– 6 analog alternate inputs
te c– 10 to 14 alternate functions
le u– EMI filtering
ds Programmable watchdog (WDG)
so ros One or two 16-bit Timers, each featuring:
b P– 2 Input Captures
- O te– 2 Output Compares
) le– External Clock input (on Timer A only)
t(s o– PWM and Pulse Generator modes
ss Synchronous Serial Peripheral Interface (SPI)
c bs 8-bit Analog-to-Digital converter (6 channels)
u O(ST72212 and ST72213 only)
rod -s 8-bit Data Manipulation
P t(s)s 63 Basic Instructions
s 17 main Addressing Modes
lete ucs 8 x 8 Unsigned Multiply Instruction
ds True Bit Manipulation
so ros Complete Development Support on PC/DOS-
b PWINDOWSTM Real-Time Emulator
O tes Full Software Package on DOS/WINDOWSTM
(C-Compiler, Cross-Assembler, Debugger)
PSDIP32
CSDIP32W
SO28
(See ordering information at the end of datasheet)
oleDevice Summary
bsFeatures
OProgram Memory- bytes
ST72101G1
4K
ST72101G2
8K
ST72213G1
4K
ST72212G2
8K
RAM (stack) - bytes
256 (64)
16-bit Timers
one one one two
ADC
no no yes yes
Other Peripherals
Watchdog, SPI
Operating Supply
3 to 5.5 V
CPU Frequency
8MHz max (16MHz oscillator) - 4MHz max over 85°C
Temperature Range
- 40°C to + 125°C
Package
SO28 - SDIP32
Rev. 1.8
May 2001
1/85
1
1 page  
ST72101/ST72212/ST72213
1.2 PIN DESCRIPTION
Figure 2. ST72212 Pinout (SO28)
Figure 5. ST72212 Pinout (SDIP32)
RESET
1
32 VDD
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6
MISO/PB5
MOSI/PB4
OCMP2_A/PB3
ICAP2_A/PB2
)OCMP1_A/PB1
t(sICAP1_A/PB0
AIN5/EXTCLK_A/PC5
cAIN4/OCMP2_B/PC4
uAIN3/ICAP2_B/PC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 VSS
26
TEST/VP
1)
P
25 PA0
24 PA1
23 PA2
22 PA3
21 PA4
20 PA5
19 PA6
18 PA7
17 PC0/ICAP1_B/AIN0
16 PC1/OCMP1_B/AIN1
15 PC2/CLKOUT/AIN2
rod )1) V on EPROM/OTP only
PP
P t(s(1)V
EPROM/OTP l
Figure 3. ST72213 Pinout (SO28)
lete ducRESET
so roOSCIN
b POSCOUT
SS/PB7
- O teSCK/PB6
) leMISO/PB5
MOSI/PB4
t(s oOCMP2_A/PB3
sICAP2_A/PB2
c bOCMP1_A/PB1
u OICAP1_A/PB0
d -AIN5/EXTCLK_A/PC5
ro )AIN4/PC4
P t(sAIN3/PC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28 VDD
27 VSS
26 TEST/VPP1)
25 PA0
24 PA1
23 PA2
22 PA3
21 PA4
20 PA5
19 PA6
18 PA7
17 PC0/AIN0
16 PC1/AIN1
15 PC2/CLKOUT/AIN2
te c1) V on EPROM/OTP only
PP
le duFigure 4. ST72101 Pinout (SO28)
bso ProRESET
O teOSCIN
leOSCOUT
SS/PB7
soSCK/PB6
b MISO/PB5
O MOSI/PB4
1
2
3
4
5
6
7
28 VDD
27 VSS
26 TEST/VPP1)
25 PA0
24 PA1
23 PA2
22 PA3
OSCIN
OSCOUT
SS/PB7
SCK/PB6
MISO/PB5
MOSI/PB4
NC
NC
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/OCMP2_B/PC4
AIN3/ICAP2_B/PC3
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
31 VSS
30 TEST/VPP1)
29 PA0
28 PA1
27 PA2
26 PA3
25 NC
24 NC
23 PA4
22 PA5
21 PA6
20 PA7
19 PC0/ICAP1_B/AIN0
18 PC1/OCMP1_B/AIN1
17 PC2/CLKOUT/AIN2
1) V on EPROM/OTP only
PP
Figure 6. ST72213 Pinout (SDIP32)
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6
MISO/PB5
MOSI/PB4
NC
NC
OCMP2_A/PB3
ICAP2_A/PB2
OCMP1_A/PB1
ICAP1_A/PB0
AIN5/EXTCLK_A/PC5
AIN4/PC4
AIN3/PC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32 VDD
31 VSS
30 TEST/VPP1)
29 PA0
28 PA1
27 PA2
26 PA3
25 NC
24 NC
23 PA4
22 PA5
21 PA6
20 PA7
19 PC0/AIN0
18 PC1/AIN1
17 PC2/CLKOUT/AIN2
1) V on EPROM/OTP only
PP
Figure 7. ST72101 Pinout (SDIP32)
RESET
OSCIN
OSCOUT
SS/PB7
SCK/PB6
MISO/PB5
MOSI/PB4
NC
NC
1
2
3
4
5
6
7
8
9
32 VDD
31 VSS
30 TEST/VPP1)
29 PA0
28 PA1
27 PA2
26 PA3
25 NC
24 NC
OCMP2_A/PB3
8
21 PA4
OCMP2_A/PB3 10
23 PA4
ICAP2_A/PB2
9
20 PA5
ICAP2_A/PB2 11
22 PA5
OCMP1_A/PB1
10
19 PA6
OCMP1_A/PB1 12
21 PA6
ICAP1_A/PB0
11
18 PA7
ICAP1_A/PB0 13
20 PA7
EXTCLK_A/PC5
12
17 PC0
EXTCLK_A/PC5 14
19 PC0
PC4 13
16 PC1
PC4 15
18 PC1
PC3 14
15 PC2/CLKOUT
PC3 16
17 PC2/CLKOUT
1) V on EPROM/OTP only
PP
1) V on EPROM/OTP only
PP
5/85
5
5 Page 
ST72101/ST72212/ST72213
Table 5. Hardware Register Memory Map
Address
Block
Name
Register
Label
Register name
Reset Status
Remarks
0000h
0001h
0002h
Port C
PCDR
PCDDR
PCOR
Data Register
Data Direction Register
Option Register
00h R/W
00h R/W
00h R/W
0003h
Reserved Area (1 Byte)
0004h
PBDR
Data Register
00h R/W
0005h
Port B
PBDDR
Data Direction Register
00h R/W
0006h
0007h
t(s)0008h
0009h
c000Ah
du000Bh to
ro )001Fh
P t(s0020h
te c0021h
le du0022h
so ro0023h
b P0024h
- O te0025h to
0030h
t(s) ole0031h
s0032h
c b0033h
u O0034h-0035h
Port A
SPI
WDG
rod ) -0036h-0037h
te P ct(s0038h-0039h Timer A
le du003Ah-003Bh
bso Pro003Ch-003Dh
O lete003Eh-003Fh
Obso0040h
PBOR
PADR
PADDR
PAOR
MISCR
SPIDR
SPICR
SPISR
WDGCR
TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR
Option Register
Reserved Area (1 Byte)
Data Register
Data Direction Register
Option Register
Reserved Area (21 Bytes)
Miscellaneous Register
Data I/O Register
Control Register
Status Register
Watchdog Control register
Reserved Area (12 Bytes)
Control Register2
Control Register1
Status Register
Input Capture1 High Register
Input Capture1 Low Register
Output Compare1 High Register
Output Compare1 Low Register
Counter High Register
Counter Low Register
Alternate Counter High Register
Alternate Counter Low Register
Input Capture2 High Register
Input Capture2 Low Register
Output Compare2 High Register
Output Compare2 Low Register
Reserved Area (1 Byte)
00h
00h
00h
00h
00h
xxh
0xh
00h
7Fh
00h
00h
00h
xxh
xxh
80h
00h
FFh
FCh
FFh
FCh
xxh
xxh
80h
00h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Read Only
R/W
R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W
11/85
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ST72212G2.PDF ] | |
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