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PDF UT54ACTQ16374 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACTQ16374 | |
| Descripción | RadHard CMOS 16-bit D Flip-Flop TTL | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT54ACTQ16374
RadHard CMOS 16-bit D Flip-Flop TTL Inputs, and
Three-State Outputs
Datasheet
May 16, 2012
www.aeroflex.com/radhard
FEATURES
16 non-inverting D flip-flops with three-state outputs
Guaranteed simultaneously switching noise level and dy-
namic threshold performance
Buffered positive edge-triggered clock
Separate control logic for each byte
Guaranteed pin-to-pin output skew
0.6m Commercial RadHardTM CMOS
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU Onset LET >95 MeV -cm2/mg
High speed, low power consumption
Output source/sink 24mA
Standard Microcircuit Drawing 5962-06245
- QML compliant part
Package:
- 48-lead flatpack, 25 mil pitch (.390 x .640)
DESCRIPTION
The 16-bit wide UT54ACTQ16374 D flip-flop is built using
Aeroflex’s Commercial RadHardTM epitaxial CMOS technolo-
gy and is ideal for space applications. This high-speed, low pow-
er UT54ACTQ16374 D flip-flop is designed for bus oriented
applications. A buffered clock (CP) and Output Enable (OE) are
common to each byte and can be shorted together for full 16-bit
operation. The UT54ACTQ16374 are particularly suitable for
implementing buffer registers, I/O ports, bidirectional bus driv-
ers and working registers. Each flip-flop will store the state of
their indivdual D inputs (In) that meet the setup and hold re-
quirements on the low-to-high clock (CPn) transition. With the
Output Enable (OEn) low, the contents of the flip-flops are avail-
able at the output. When OEn is high, the outputs go to high
impedance state. Operation of OEn input does not affect the state
of the D flip-flops.
PIN DESCRIPTION
Pin Names
Description
OEn
Output Enable Input (Active Low)
CPn Clock Pulse Input
I0-I15
O0-O15
Inputs
Outputs
LOGIC SYMBOL
OE1 (1)
CP1 (48)
OE2 (24)
CP2 (25)
(47)
I0
I1 (46)
(44)
I2
(43)
I3
(41)
I4
(40)
I5
(38)
I6
(37)
I7
(36)
I8 (35)
I9
(33)
I10
(32)
I11
(30)
I12
(29)
I13
(27)
I14
(26)
I15
EN2
C1
EN4
C3
1D
3D
(2)
2 O0
(3)
O1
(5)
O2
(6)
O3
(8)
O4
(9)
(11) O5
O6
(12)
(13) O7
4 (14) O8
O9
(16)
O10
(17)
O11
(19)
O12
(20)
(22)
O13
O14
(23)
O15
1
1 page  
RADIATION HARDNESS SPECIFICATIONS 1
PARAMETER
Total Dose
SEL Immune
LIMIT
1.0E5
>108
SEU Onset LET
>95
Neutron Fluence2
1.0E14
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
UNITS
rad(Si)
MeV-cm2/mg
MeV-cm2/mg
n/cm2
ABSOLUTE MAXIMUM RATINGS1
SYMBOL
PARAMETER
LIMIT (Mil only)
UNITS
VI/O
Voltage any pin during operation
-.3 to VDD +.3
V
VDD
TSTG
TJ
JC
II
Supply voltage
Storage Temperature range
Maximum junction temperature
Thermal resistance junction to case
DC input current
-0.3 to 6.0
-65 to +150
+175
20
10
V
C
C
C/W
mA
PD Maximum power dissipation
310 mW
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
VDD
VIN
TC
tINRISE
tINFALL
PARAMETER
Supply voltage
Input voltage any pin
Temperature range
Maximum input rise or fall time
(VIN transitioning between VIL (max) and VIH (min))
LIMIT
4.5 to 5.5
0 to VDD
-55 to + 125
20
UNITS
V
V
C
ns
5
5 Page 
PACKAGE
NOTE:
1. Seal ring is connected to VSS.
2. Units are in inches.
3. All exposed metalized areas must be gold plated 100 to 225 microinches thick. Dyer electroplated nickel
undercoating 100 to 350 microinches per MIL-PRF-38535.
Figure 1. 48-Lead Flatpack
11 Page | ||
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| PDF Descargar | [ Datasheet UT54ACTQ16374.PDF ] | |
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