PDF UT54ACS164646S Data sheet ( Hoja de datos )

Número de pieza	UT54ACS164646S
Descripción	Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver
Fabricantes	Aeroflex Circuit Technology
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Standard Products UT54ACS164646S Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver Datasheet May 17, 2012 www.aeroflex.com/16bitLogic FEATURES  Flexible voltage operation - 5V bus to 3.3V bus - 3.3V bus to 5V bus - 5V bus to 5V bus - 3.3V bus to 3.3V bus  Independent registers for A and B buses  Multiplexed real-time and stored data  Flow-through architecture optimizes PCB layout  Cold- and Warm-sparing - 750k minimum input impedance power-off - Guranteed output tri-state while one power supply is "off" and the other is "on"  Schmitt trigger inputs to filter noisy signals  All inputs are 5V tolerant regardless of power supply voltage  m CRH CMOS Technology  Operational Environment: - Total dose: 100K rad(Si) - Single Event Latchup immune>110 MeV-cm2/mg - SEU Onset LET >75 MeV-cm2/mg  High speed, low power consumption  Available QML Q or V processes  Standard Microcircuit Drawing: 5962-06234  Package: - 56-pin ceramic flatpack PIN DESCRIPTION Pin Names Description xOE xDIR Output Enable Input (Active Low) Direction Control Inputs xAx Side A Inputs or 3-State Outputs (3.3V Port) xBx Side B Inputs or 3-State Outputs (5V Port) xSAB Select real-time or stored A bus data to B bus xSBA xCLKAB Select real-time or stored B bus data to A bus Store A bus data xCLKBA Store B bus data DESCRIPTION The UT54ACS164646S is a 16-bit, MultiPurpose, registered, level shifting, bus transceiver consisting of D-type flip-flops, control circuitry, and 3-state outputs arranged for multiplexed transmission of data directly from the data bus or from the internal storage registers. The high-speed, low power UT54ACS164646S transceiver is designed to perform multi- ple functions including: asynchronous two-way communica- tion, signal buffering, voltage translation, cold- and warm- sparing. The device can be used as two independant 8-bit transceivers or one 16-bit transceiver. Data on the A or B bus is clocked into the registers on the rising edge of the appropri- ate clock (xCLKAB or xCLKBA) input. With either VDD sup- ply equal to zero volts, the UT54ACS164646S outputs and inputs present a minimum impedance of 750k making it ideal for “cold-spare” and "warm-spare" applications. By vir- tue of its flexible power supply interface, the UT54ACS164646S may operate as a 3.3-volt only, 5-volt only, or mixed 3.3V/5V bus transceiver. The Output-enable (xOE) and direction-control (xDIR) inputs are provided to control the tri-state function and input/output direction of the transceiver respectively. The select controls (xSAB and xSBA) select whether stored register data or real- time data is driven to the outputs as determined by the xDIR inputs. The circuitry used for select control eliminates the typ- ical decoding glitch that occurs in a multiplexer during the transition between stored and real-time data. Regardless of the selected operating mode ("real-time" or "recall"), a rising edge on the port input clocks (xCLKAB and xCLKBA) will latch the corresponding I/O states into their respective registers. Furthermore, when a data port is isolated (xOE = high), A-port data may be stored into its corresponding register while B-port data may be independantly stored into its corresponding regis- ters. Therefore, when an output function is disabled, the input function is still enabled and may be used to store and transmit data. Lastly, only one of the two buses, xA-port or xB-port, may be driven at a time. 1 1 page OPERATIONAL ENVIRONMENT 1 PARAMETER Total Dose SEL LET Threshold LIMIT 1.0E5 >110 SEU Onset LET Threshold4 SEU Error Rate2 Neutron Fluence3 >97 @4.5V, >74@ 3.0V Immune @4.5V, 6.3E-10 @3.0V 1.0E14 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Adams 90% worst case particle environment, geosynchronous orbit, 100mils of Aluminum shielding 3. Not tested, inherent of CMOS technology. 4. Core logic is driven by VDDB. UNITS rad(Si) MeV-cm2/mg MeV-cm2/mg errors/bit-day n/cm2 ABSOLUTE MAXIMUM RATINGS1 SYMBOL PARAMETER LIMIT (Mil only) UNITS VI/OB (Port B)2 VI/OA (Port A)2 VDDB VDDA TSTG TJ JC II PD Voltage any pin Voltage any pin Supply voltage Supply voltage Storage Temperature range Maximum junction temperature Thermal resistance junction to case DC input current Maximum power dissipation -0.3 to 6.0 -0.3 to 6.0 -0.3 to 6.0 -0.3 to 6.0 -65 to +150 +175 20 10 250 V V V V C C C/W mA mW Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. For cold spare mode (VDDx = VSS +/- 0.3V), VI/Ox may be -0.3V to the maximum recommended operating VDDx + 0.3V. 5 5 Page AC ELECTRICAL CHARACTERISTICS1 (Port A = Port B, 5 Volt Operation) (VDDB = 5V 10%; VDDA = 5V +10%) (TC = -55C to +125C); Unless otherwise noted, Tc is per the temperature ordered SYMBOL PARAMETER MINIMUM MAXIMUM UNIT tPLH1 tPHL1 tPLH2 tPHL2 tPLH32 tPHL32 tPLH42 tPHL42 tPZH1 tPZL1 tPLZ1 tPHZ1 tPZH23 tPZL23 tPLZ23 tPHZ23 tSKEW4 tOST5 tPART6 Propagation delay Data to Bus Propagation delay Data to Bus xCLKAB or xCLKBA to Bus xCLKAB or xCLKBA to Bus xSAB or xSBA  to Bus xSAB or xSBA to Bus xSBA or xSAB to Bus xSBA or xSAB to Bus Output enable time xOE to Bus Output enable time xOE to Bus Output disable time xOE to Bus high impedance Output disable time xOE to Bus high impedance Output enable time xDIR to Bus Output enable time xDIR to Bus Output disable time xDIR to Bus high impedance Output disable time xDIR to Bus high impedance Skew between outputs Differential output skew Part to part skew 3.5 7.5 ns 3.5 7.5 ns 4 9 ns 4 9 ns 3 8 ns 3 8 ns 3 8 ns 3 8 ns 3.5 9 ns 3.5 9 ns 3 8 ns 3 8 ns 3 11 ns 3 11 ns 3 11 ns 3 11 ns 600 ps 1500 ps 500 ps Notes: For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25oC per MIL-STD-883 Method 1019, Condition A up to the maximum TID level procured. 1. All specifications valid for radiation dose  1E5 rads(Si) per MIL-STD-883, Method 1019. 2. These parameters are measured with the internal output state of the storage register opposite to that of the bus input. 3. xDIR to bus times are guaranteed by design, but not tested. xOE to bus times are tested. 4. Output skew is defined as a comparison of any two output transitions of the same type at the saame temperature and voltage for the same port within the same byte: 1A1 through 1A8 are compared high-to-low versus high-to-low and low-to-high versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are compared, and 2B1 through 2B8 are compared. 5. Differential output skew is defined as a comparison of any two output transitions of opposite types on the same type at the same temperature and voltage for the same port within the same byte: 1A1 through 1A8 are compared high-to-low versus low-to-high; similarly 1B1 through 1B8 are compared, 2A1 through 2A8 are compared, and 2B1 through 2B8 are compared. 6. Guaranteed by characterization, but not tested. 11 11 Page

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