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PDF UT54ACTS164E Data sheet ( Hoja de datos )
| Número de pieza | UT54ACTS164E | |
| Descripción | 8-Bit Shift Registers | |
| Fabricantes | Aeroflex Circuit Technology | |
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UT54ACS164E/UT54ACTS164E
8-Bit Shift Registers
October, 2008
www.aeroflex.com/Logic
FEATURES
• AND-gated (enable/disable) serial inputs
• Fully buffered clock and serial inputs
• Direct clear
• 0.6μm CRH CMOS Process
- Latchup immune
• High speed
• Low power consumption
• Wide operating power supply from 3.0V to 5.5V
• Available QML Q or V processes
• 14-lead flatpack
DESCRIPTION
The UT54ACS164E and the UT54ACTS164E are 8-bit shift
registers which feature AND-gated serial inputs and an asyn-
chronous clear. The gated serial inputs (A and B) permit com-
plete control over incoming data. A low at either input inhibits
entry of new data and resets the first flip-flop to the low level
at the next clock pulse. A high-level at both serial inputs sets
the first flip-flop to the high level at the next clock pulse. Data
at the serial inputs may be changed while the clock is high or
low, providing the minimum setup time requirements are met.
Clocking occurs on the low-to-high-level transition of the clock
input.
The devices are characterized over full HiRel temperature range
of -55°C to +125°C.
PINOUT
A
B
QA
QB
QC
QD
VSS
14-Lead Flatpack
Top View
1 14
2 13
3 12
4 11
5 10
69
78
VDD
QH
QG
QF
QE
CLR
CLK
FUNCTION TABLE
CLR
INPUTS
CLK A
LXX
HLX
H↑H
H↑ L
H↑X
OUTPUTS
B QA
QB ... QH
XLLL
X
QA0
QB0
QH0
H
H
QAn
QGn
X
L
QAn
QGn
L
L
QAn
QGn
Notes:
1. QA0, QB0, QH0 = the level of QA, QB or QH, respectively, before the indicated
steady-state input conditions were established.
2. QAn and QGn = the level of QA or QG before the most recent ↑ transition of
the clock; indicates a one-bit shift.
LOGIC SYMBOL
(9)
CLR
(8)
CLK
A (1)
(2)
B
SRG8
R
C1/
&
1D
(3)
QA
(4)
(5) QB
(6) QC
(10) QD
(11) QE
(12) QF
(13) QG
QH
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1
1 page  
DC ELECTRICAL CHARACTERISTICS FOR THE UT54ACTS164E7
( VDD = 3.0V to 5.5V; VSS = 0V6; -55°C < TC < +125°C)
SYMBOL
Description
VIL Low-level input voltage 1
CONDITION
VIH High-level input voltage 1
IIN
VOL
VOH
IOS
Input leakage current
Low-level output voltage 3
High-level output voltage 3
Short-circuit output current 2 ,4
VIN = VDD or VSS
IOL = 6mA
IOL = 8mA
IOH = -6mA
IOH = -8mA
VO = VDD and VSS
VDD
3.0V
5.5V
3.0V
5.5V
5.5V
3.0V
4.5V
3.0V
4.5V
3.0V
5.5V
MIN
2.0
2.75
-1
2.4
3.15
-100
-200
MAX
0.8
0.8
UNIT
V
V
1 μA
0.4 V
0.4 V
V
V
100 mA
200
IOL Low level output current10
VIN = VDD or VSS
VOL = 0.4V
3.0V 6
5.5V 8
mA
IOH High level output current10
Ptotal Power dissipation 2, 8, ,9
VIN = VDD or VSS
VOH = VDD-0.4V
CL = 50pF
IDDQ
ΔIDDQ
CIN
COUT
Quiescent Supply Current
Quiescent Supply Current Delta
Input capacitance 5
Output capacitance 5
VIN = VDD or VSS
For input under test
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
ƒ = 1MHz
ƒ = 1MHz
3.0V
5.5V
5.5V
3.0V
5.5V
5.5V
0V
0V
-6 mA
-8
1.9 mW/
0.76 MHz
10 μA
1.6 mA
15 pF
15 pF
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, - 50%,
as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are guaranteed
to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si) per MIL-STD-883 Method 1019 Condition A and section 3.11.2.
8. Power does not include power contribution of any TTL output sink current
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
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| PDF Descargar | [ Datasheet UT54ACTS164E.PDF ] | |
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