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PDF UT54ACTS280 Data sheet ( Hoja de datos )
| Número de pieza | UT54ACTS280 | |
| Descripción | 9-Bit Parity Generators/Checkers | |
| Fabricantes | Aeroflex Circuit Technology | |
| Logotipo |  |
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Standard Products
UT54ACS280/UT54ACTS280
9-Bit Parity Generators/Checkers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
Generates either odd or even parity for nine data lines
Cascadable for n-bits parity
1.2μ CMOS
- Latchup immune
High speed
Low power consumption
Single 5 volt supply
Available QML Q or V processes
Flexible package
- 14-pin DIP
- 14-lead flatpack
UT54ACS280 - SMD 5962-96582
UT54ACTS280 - SMD 5962-96583
DESCRIPTION
The UT54ACS280 and the UT54ACTS280 are 9-bit parity gen-
erators/checkers that use high-performance circuitry and fea-
tures odd and even outputs to facilitate operation of either odd
or even parity application. The word-length capability is easily
expanded by cascading.
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
NUMBER OF INPUTS A THRU I
THAT ARE HIGH
0,2,4,6,8
1,3,5,7,9
OUTPUT
Σ EVEN
H
L
Σ ODD
L
H
LOGIC SYMBOL
PINOUTS
14-Pin DIP
Top View
G
H
NC
I
∑ EVEN
∑ ODD
VSS
1 14
2 13
3 12
4 11
5 10
69
78
VDD
F
E
D
C
B
A
G
H
NC
I
∑ EVEN
∑ ODD
VSS
14-Lead Flatpack
Top View
1 14
2 13
3 12
4 11
5 10
69
78
(8)
A
(9)
B
(10)
C
(11)
D
(12)
E
(13)
F
(1)
G
(2)
H
I (4)
2k
(5) ∑
EVEN
(6) ∑
ODD
Note:
1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC
Publication 617-12.
1
VDD
F
E
D
C
B
A
1 page  
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
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| PDF Descargar | [ Datasheet UT54ACTS280.PDF ] | |
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