K4D261638K-LC50 Datasheet PDF - Samsung
Part Number | K4D261638K-LC50 | |
Description | 128Mbit GDDR SDRAM | |
Manufacturers | Samsung | |
Logo | ||
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128M GDDR SDRAM
128Mbit GDDR SDRAM
2M x 16Bit x 4 Banks
Graphic Double Data Rate
Synchronous DRAM
Revision 1.3
July 2007
Notice
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
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Rev. 1.3 July 2007
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K4D261638K
128M GDDR SDRAM
5.0 INPUT/OUTPUT FUNCTIONAL DESCRIPTION
Symbol
Type
Function
CK, CK*1
Input
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except DQ’s and DM’s that are
sampled on both edges of the DQS.
CKE
Input
Activates the CK signal when high and deactivates the CK signal when low. By deactivating
the clock, CKE low indicates the Power down mode or Self refresh mode.
CS enables the command decoder when low and disabled the command decoder when high.
CS
Input
When the command decoder is disabled, new commands are ignored but previous operations
continue.
RAS
Input
Latches row addresses on the positive going edge of the CK with RAS low. Enables row
access & precharge.
CAS
Input
Latches column addresses on the positive going edge of the CK with CAS low. Enables col-
umn access.
WE
Input
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
LDQS,UDQS
Input/Output
Data input and output are synchronized with both edge of DQS.
For the x16, LDQS corresponds to the data on DQ0-DQ7 ; UDQS corresponds to the data on
DQ8-DQ15.
LDM,UDM
Input
Data in Mask. Data In is masked by DM Latency=0 when DM is
high in burst write. For the x16, LDM corresponds to the data on DQ0-DQ7 ; UDM correspons
to the data on DQ8-DQ15.
DQ0 ~ DQ15
Input/Output
Data inputs/Outputs are multiplexed on the same pins.
BA0, BA1
Input
Selects which bank is to be active.
A0 ~ A11
Input
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA0 ~ RA11, Column addresses : CA0 ~ CA8.
VDD/VSS
Power Supply
Power and ground for the input buffers and core logic.
VDDQ/VSSQ
Power Supply
Isolated power supply and ground for the output buffers to provide improved noise immunity.
VREF
Power Supply
Reference voltage for inputs, used for SSTL interface.
NC/RFU
No connection/
Reserved for future use
This pin is recommended to be left "No connection" on the device
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
For any applications using the single ended clocking, apply VREF to CK pin.
- 5 /19 -
Rev. 1.3 July 2007
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