74HCU04BQ Datasheet PDF - NXP Semiconductors
Part Number | 74HCU04BQ | |
Description | Hex unbuffered inverter | |
Manufacturers | NXP Semiconductors | |
Logo | ||
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Preview 1 page No Preview Available ! 74HCU04
Hex unbuffered inverter
Rev. 7 — 8 December 2015
Product data sheet
1. General description
The 74HCU04 is a hex unbuffered inverter. Inputs include clamp diodes. This enables the
use of current limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Complies with JEDEC standard JESD7A
Balanced propagation delays
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number Package
Temperature
range
Name
Description
Version
74HCU04D
40 C to +125 C SO14
plastic small outline package; 14 leads; body width 3.9 mm SOT108-1
74HCU04DB 40 C to +125 C SSOP14
plastic shrink small outline package; 14 leads; body width SOT337-1
5.3 mm
74HCU04PW 40 C to +125 C TSSOP14 plastic thin shrink small outline package; 14 leads;
body width 4.4 mm
SOT402-1
74HCU04BQ
40 C to +125 C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin SOT762-1
quad flat package; no leads; 14 terminals;
body 2.5 3 0.85 mm
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NXP Semiconductors
74HCU04
Hex unbuffered inverter
10. Dynamic characteristics
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); For test circuit see Figure 7.
Symbol Parameter
Conditions
25 C
tpd
propagation delay
nA to nY; see Figure 6
VCC = 2.0 V; CL = 50 pF
VCC = 4.5 V; CL = 50 pF
VCC = 5.0 V; CL = 15 pF
VCC = 6.0 V; CL = 50 pF
tt transition time
see Figure 6
VCC = 2.0 V; CL = 50 pF
VCC = 4.5 V; CL = 50 pF
VCC = 6.0 V; CL = 50 pF
CPD power dissipation per inverter; VI = GND to VCC
capacitance
Typ
[1]
19
7
5
6
[2]
19
7
6
[3] 10
Max
70
14
-
12
75
15
13
-
40 C to
+85 C
Max
40 C to Unit
+125 C
Max
90 105 ns
18 21 ns
- - ns
15 18 ns
95 110 ns
19 22 ns
16 19 ns
- - pF
[1] tpd is the same as tPHL, tPLH.
[2] tt is the same as tTHL, tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD = CPD VCC2 fi N + (CL VCC2 fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CL VCC2 fo) = sum of outputs.
74HCU04
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 8 December 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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