EDI88128C Datasheet PDF - White Electronic Designs
Part Number | EDI88128C | |
Description | 128Kx8 MONOLITHIC SRAM | |
Manufacturers | White Electronic Designs | |
Logo | ||
There is a preview and EDI88128C download ( pdf file ) link at the bottom of this page. Total 8 Pages |
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EDI88128C
128Kx8 MONOLITHIC SRAM, SMD 5962-89598
FEATURES
Access Times of 70, 85, 100ns
Available with Single Chip Selects (EDI88128) or
Dual Chip Selects (EDI88130)
2V Data Retention (LP Versions)
CS# and OE# Functions for Bus Control
TTL Compatible Inputs and Outputs
Fully Static, No Clocks
Organized as 128Kx8
Industrial, Military and Commercial Temperature
Ranges
Thru-hole and Surface Mount Packages JEDEC
Pinout
• 32 pin Ceramic DIP, 0.6 mils wide (Package 9)
• 32 lead Ceramic SOJ (Package 140)
Single +5V (±10%) Supply Operation
The EDI88128C is a high speed, high performance,
Monolithic CMOS Static RAM organized as 128Kx8.
The device is also available as EDI88130C with an
additional chip select line (CS2) which will automatically
power down the device when proper logic levels are
applied.
The second chip select line (CS2) can be used to provide
system memory security during power down in non-battery
backed up systems and simplifiy decoding schemes in
memory banking where large multiple pages of memory
are required.
The EDI88128C and the EDI88130C have eight bi-
directional input-output lines to provide simultaneous
access to all bits in a word. An automatic power down
feature permits the on-chip circuitry to enter a very low
standby mode and be brought back into operation at a
speed equal to the address access time.
Low power versions, EDI88128LP and EDI88130LP, offer
a 2V data retention function for battery back-up opperation.
Military product is available compliant to Appendix A of
MIL-PRF-38535.
FIGURE 1 – PIN CONFIGURATION
32 DIP
32 SOJ
Top View
NC 1
A16 2
A14 3
A12 4
A7 5
A6 6
A5 7
A4 8
A3 9
A2 10
A1 11
AØ 12
I/OØ 13
I/O1 14
I/O2 15
VSS 16
32 VCC
31 A15
30 NC/CS2*
29 WE#
28 A13
27 A8
26 A9
25 A11
24 OE#
23 A10
22 CS1#
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
PIN DESCRIPTION
I/O0-7
Data Inputs/Outputs
A0-16
Address Inputs
WE# Write Enable
CS1#, CS2
Chip Selects
OE# Output Enable
VCC Power (+5V ±10%)
VSS Ground
NC Not Connected
BLOCK DIAGRAM
* Pin 30 is NC for 88128 or CS2 for 88130.
WE#
CS1#
CS2
OE#
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
1 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com
|
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White Electronic Designs
EDI88128C
ADDRESS
DATA I/O
FIGURE 2 – TIMING WAVEFORM — READ CYCLE
tAVAV
ADDRESS 1
ADDRESS 2
tAVQV
tAVQX
DATA 1
DATA 2
READ CYCLE 1 (WE# HIGH; OE#, CS# LOW)
ADDRESS
CS1#
CS2
OE#
DATA I/O
tAVAV
tAVQV
tELQV
tELQX
tSHQV
tSHQX
tGLQV
tGLQX
READ CYCLE 2 (WE# HIGH)
tEHQZ
tSLQZ
tGHQZ
FIGURE 3 – WRITE CYCLE 1
ADDRESS
WE#
tAVWL
tAVAV
tAVWH
tWLWH
tWHAX
CS1#
CS2
DATA IN
DATA OUT
tELWH
tSHWH
tWLQZ
tDVWH
tWHQX
tWHDX
DATA VALID
HIGH Z
WRITE CYCLE 1 - LATE WRITE, WE# CONTROLLED
FIGURE 4 – WRITE CYCLE 2
WRITE CYCLE 3
ADDRESS
WE#
CS1#
tAVEL
tAVAV
tWLEH
tELEH
tEHAX
ADDRESS
WE#
CS1#
tAVSH
tAVAV
tWLSL
tSHSL
tSLAX
CS2
DATA IN
tDVEH
tEHDX
DATA VALID
WRITE CYCLE 2 - EARLY WRITE, CS1# CONTROLLED
CS2
DATA IN
tDVSL
tSLDX
DATA VALID
WRITE CYCLE 3 - EARLY WRITE, CS2 CONTROLLED
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
April 2005
Rev. 17
5 White Electronic Designs Corporation • (602) 437-1520 •www.whiteedc.com
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for EDI88128C electronic component. |
Information | Total 8 Pages | |
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