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PDF MAX14611 Data sheet ( Hoja de datos )
| Número de pieza | MAX14611 | |
| Descripción | Quad Bidirectional Low-Voltage Logic-Level Translator | |
| Fabricantes | Maxim Integrated | |
| Logotipo |  |
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EVALUATION KIT AVAILABLE
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
General Description
The MAX14611 is a quad bidirectional logic-level transla-
tor that provides the level shifting necessary to allow data
transfer in a multivoltage system. Externally applied volt-
ages, VCC and VL, set the logic levels on either side of
the device. A low-voltage logic signal present on the VL
side of the device appears as a high-voltage logic signal
on the VCC side of the device, and vice-versa.
The device is ideal for I2C bus as well as MDIO bus appli-
cations where open-drain operation is often required. The
device features a three-state output mode (TS). Drive TS
high to connect the pullup to the powered I/O port. This
allows for continuous, undisrupted I2C operation on the
powered side of the device while the level translation
function is off. The MAX14611 is a pin-to-pin compatible
upgrade to the MAX3378E in the TDFN package.
The MAX14611 features enhanced high-electrostatic-
discharge (ESD) protection on all I/OVCC_ ports up to
±6kV HBM. The device operates over the -40NC to +85NC
extended temperature range and is available in 3mm x
3mm, 14-pin TDFN and 4.9mm x 5.1mm, 14-pin TSSOP
packages.
Applications
SPI, I2C, and MDIO
Level Translation
Low-Voltage ASIC
Level Translation
Portable Electronics
Mobile Phones
POS Systems
Telecommunications
Equipment
Benefits and Features
S Improved Interoperability
Meets I2C Specifications
10kI Internal Pullup Resistor
Pin-to-Pin Compatible with the MAX3377E and
the MAX3378E
0.9V Operation on Low Voltage Supply
S Robust Logic-Level Translation
±0.5V Tolerances on All Pins
±6kV Human Body Model ESD Protection on
I/OVCC_ Lines
Thermal Short-Circuit Protection
Short to Ground Fault Protection on All Pins
-40NC to +85NC Operating Temperature Range
S Increased Design Flexibility
Ultra-Low Supply Current
Pullup Resistor Enabled with a Single Power
Supply when TS = High
10I (max) Transmission Gate FET
Small, 14-Pin, 3.0mm x 3.0mm TDFN Package
and 14-Pin, 4.9mm x 5.1mm TSSOP Package
Ordering Information appears at end of data sheet.
Typical Operating Circuit
+1.8V
+1.8V SYSTEM
CONTROLLER
DATA
0.1µF
VL VCC
TS
MAX14611
I/OVL_
I/OVCC_
+3.3V
1µF
+3.3V
SYSTEM
DATA
For related parts and recommended products to use with this part, refer to www.maximintegrated.com/MAX14611.related.
For pricing, delivery, and ordering information, please contact Maxim Direct at
1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
19-6276; Rev 0; 4/12
1 page  
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
VL VCC
VL VCC
TS
RS MAX14611
50I
I/OVL_
I/OVCC_
GND
CI/OVCC_
RL
tRVCC
90%
50%
10%
tPDLH
50%
tFVCC
90%
50%
50%
tPDHL
10%
Figure 1. Push-Pull Driving I/OVL_
VL VCC
VL VCC
1kI
TS
MAX14611
1kI
tRVCC
90%
I/OVL_
I/OVCC_
GND
CI/OVCC_
RL
50%
50%
10%
tPDLH
Figure 2. Open-Drain Driving I/OVL_
tFVCC
90%
50%
50%
tPDHL
10%
Maxim Integrated
5
5 Page 
MAX14611
Quad Bidirectional Low-Voltage
Logic-Level Translator
Functional Diagram
VL
PU1
I/OVL_
MAX14611
TS
ONE-SHOT
BLOCK
ONE-SHOT
BLOCK
EN CONTROL
BLOCK
GATE
DRIVE
N
VCC
PU2
I/OVCC_
Detailed Description
The MAX14611 ESD-protected level translator provides
the level shifting necessary to allow data transfer in a
multivoltage system. Externally applied voltages, VCC
and VL, set the logic levels on either side of the device.
A low-voltage logic signal present on the VL side of the
device appears as a high-voltage logic signal on the VCC
side of the device, and vice-versa.
The MAX14611 bidirectional level translator uti-
lizes a transmission-gate based design (see the
Functional Diagram) to allow data translation in either
direction (VL ↔ VCC) on any single data line. The device
accepts VL from +0.9V to +5.0V and VCC from +1.65V
to +5.5V, making it ideal for data transfer between low-
voltage ASICs/PLDs and higher voltage systems.
The device features a three-state output mode, thermal
short-circuit protection, and Q6kV ESD protection on the
VCC side for greater protection in applications that route
signals externally.
Level Translation
For proper operation, ensure that +1.65V P VCC P +5.5V,
0.9V P VL P 5.0V, and VL P (VCC + 0.3V). It is permissible
for VL to exceed (VCC + 0.3V) during power-up sequenc-
ing. During power-supply sequencing, when VCC is
disconnected and VL is powered up, a current can be
sourced without a latchup or any damage to the device.
The maximum data rate of the MAX14611 depends
heavily on load capacitance (see the Typical Operating
Characteristics), output impedance of the driver, and
the operational voltage (see the Timing Characteristics
table).
Speed-Up Circuitry
The device features a one-shot generator that decreases
the rise time of the output. When triggered following a ris-
ing edge, MOSFETs PU1 and PU2 turn on for a short time
to pull up I/OVL_ and I/OVCC_ to their respective sup-
plies (see the Functional Diagram). This greatly reduces
the rise time and propagation delay for the low-to-high
transition.
Maxim Integrated
11
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| PDF Descargar | [ Datasheet MAX14611.PDF ] | |
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