M74HC164RM13TR Datasheet PDF - STMicroelectronics
Part Number | M74HC164RM13TR | |
Description | 8 BIT SIPO SHIFT REGISTER | |
Manufacturers | STMicroelectronics | |
Logo | ||
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8 BIT SIPO SHIFT REGISTER
s HIGH SPEED :
fMAX = 62MHz (TYP.) at VCC = 6V
s LOW POWER DISSIPATION:
ICC =4µA(MAX.) at TA=25°C
s HIGH NOISE IMMUNITY:
)VNIH = VNIL = 28 % VCC (MIN.)
t(ss SYMMETRICAL OUTPUT IMPEDANCE:
|IOH| = IOL = 4mA (MIN)
ucs BALANCED PROPAGATION DELAYS:
dtPLH ≅ tPHL
ros WIDE OPERATING VOLTAGE RANGE:
PVCC (OPR) = 2V to 6V
s PIN AND FUNCTION COMPATIBLE WITH
te74 SERIES 164
oleDESCRIPTION
sThe M74HC164 is an high speed CMOS 8 BIT
bSIPO SHIFT REGISTER fabricated with silicon
Ogate C2MOS technology.
-The M74HC164 is an 8 bit shift register with serial
t(s)data entry and an output from each of the eight
stages. Data is entered serially through one of two
cinputs (A or B), either of these inputs can be used
uas an active high enable for data entry through the
dother input. An unused input must be high, or both
roinputs connected together. Each low-to-high
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
TUBE
DIP
SOP
TSSOP
M74HC164B1R
M74HC164M1R
T&R
M74HC164RM13TR
M74HC164TTR
transition on the clock inputs shifts data one place
to the right and enters into QA the logic NAND of
the two data inputs (A x B), the data that existed
before the rising clock edge. A low level on the
clear input overrides all other inputs and clears the
register asynchronously, forcing all Q outputs low.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
Obsolete PPIN CONNECTION AND IEC LOGIC SYMBOLS
June 2003
1/13
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M74HC164
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6ns)
Test Condition
Value
Symbol
Parameter
VCC
(V)
TA = 25°C
-40 to 85°C -55 to 125°C Unit
Min. Typ. Max. Min. Max. Min. Max.
tTLH tTHL Output Transition
Time
2.0
4.5
30 75
8 15
95 110
19 22 ns
6.0 7 13 16 19
tPLH tPHL Propagation Delay 2.0
Time (CLOCK - Q) 4.5
57 160 200 240
19 32 40 48 ns
tPLH tPHL Propagation Delay
)Time (CLEAR - Q)
uct(sfMAX Maximum Clock
Frequency
ProdtW(H)
tW(L)
Minimum Pulse
Width (CLOCK)
letetW(L) Minimum Pulse
oWidth (CLEAR)
Obsts Set-up Time (A, B -
-CK)
t(s)th Hold Time (A, B -
CK)
roductREM Minimum Removal
PTime
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
2.0
4.5
6.0
leteCAPACITIVE CHARACTERISTICS
ObsoSymbol
Parameter
Test Condition
VCC
16 27 34 41
60 175 220 265
20 35 44 53 ns
17 30 37 45
6.2 18 5.0 4.2
31 53 25 21 MHz
37 62 30 25
24 75
95 110
6 15 19 22 ns
5 13 16 19
40 75
95 110
10 15 19 22 ns
9 13 16 19
50 65 75
10 13 15 ns
9 11 13
5 55
5 5 5 ns
5 55
555
5 5 5 ns
555
TA = 25°C
Value
-40 to 85°C -55 to 125°C Unit
(V) Min. Typ. Max. Min. Max. Min. Max.
CIN Input Capacitance 5.0
5 10 10 10 pF
CPD Power Dissipation
Capacitance (note 5.0
1)
99
pF
1) CPD is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. ICC(opr) = CPD x VCC x fIN + ICC
5/13
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Information | Total 13 Pages | |
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