IS31SE5001 Datasheet PDF - ISSI
| Part Number | IS31SE5001 | |
| Description | IR SENSOR | |
| Manufacturers | ISSI | |
| Logo |  |
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IS31SE5001
IR SENSOR FOR TOUCHLESS PROXIMITY
July 2013
GENERAL DESCRIPTION
The IS31SE5001 is a low-power, reflectance-based
infrared light sensor with advanced signal processing
and digital output. The sensor can detect making
touchless motion possible.
The IS31SE5001 uses one infrared LED and an
internal receiver which pick up the reflectance signal
to perform touchless motion detection. When
proximity motion happens, the flag bit in status
register will be triggered and an interrupt signal is
generated to inform the master to read the flag bit
through I2C interface.
IS31SE5001 is available in QFN-8 (2mm × 2mm). It
operates from 2.7V to 5.5V over the temperature
range of -40°C to +85°C.
FEATURES
Supply voltage from 2.7V~5.5V
400kHz I2C compatible interface
1µA shutdown current
0.6mA low supply current
Detection range can be adjusted
Integrated signal processing and digital output
Auto interrupt clear
Package in QFN-8 (2mm × 2mm)
APPLICATIONS
Smart phones/GPS/MID/PAD/MP3
Lighting/switch controller/
household electrical appliances
Toys/game machine
TYPICAL APPLICATION CIRCUIT
VBattery
7
VCC
1 F 0.1 F
VBattery
VDD
4.7k 4.7k 4.7k
Micro
Controller
100k
8
IRLED
5 IS31SE5001
SDA
RX 6
4
SCL
3
INTB
2
SDB GND 1
IRLED
IS31SE5001 IRLED
LCD
IS31SE5001 IRLED
Figure 1 Typical Application Circuit
Integrated Silicon Solution, Inc. – www.issi.com
Rev. B, 07/04/2013
1
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IS31SE5001
DETAILED DESCRIPTION
I2C INTERFACE
The IS31SE5001 uses a serial bus, which conforms to
the I2C protocol, to control the chip’s functions with two
wires: SCL and SDA. The IS31SE5001 has a 7-bit
slave address (A7:A1), followed by the R/W bit, A0. Set
A0 to “0” for a write command and set A0 to “1” for a
read command.
The complete slave address is:
Table 1 Slave Address (Write only):
Bit
A7:A1
A0
Value
1010101
1/0
The SCL line is uni-directional. The SDA line is
bi-directional (open-collector) with a pull-up resistor
(typically 4.7kΩ). The maximum clock frequency
specified by the I2C standard is 400kHz. In this
discussion, the master is the microcontroller and the
slave is the IS31SE5001.
The timing diagram for the I2C is shown in Figure 2.
The SDA is latched in on the stable high level of the
SCL. When there is no interface activity, the SDA line
should be held high.
The “START” signal is generated by lowering the SDA
signal while the SCL signal is high. The start signal will
alert all devices attached to the I2C bus to check the
incoming address against their own chip address.
The 8-bit chip address is sent next, most significant bit
first. Each address bit must be stable while the SCL
level is high.
After the last bit of the chip address is sent, the master
checks for the IS31SE5001’s acknowledge. The
master releases the SDA line high (through a pull-up
resistor). Then the master sends an SCL pulse. If the
IS31SE5001 has received the address correctly, then
it holds the SDA line low during the SCL pulse. If the
SDA line is not low, then the master should send a
“STOP” signal (discussed later) and abort the transfer.
Following acknowledge of IS31SE5001, the register
address byte is sent, most significant bit first.
IS31SE5001 must generate another acknowledge
indicating that the register address has been received.
Then 8-bit of data byte are sent next, most significant
bit first. Each data bit should be valid while the SCL
level is stable high. After the data byte is sent, the
IS31SE5001 must generate another acknowledge to
indicate that the data was received.
The “STOP” signal ends the transfer. To signal “STOP”,
the SDA signal goes high while the SCL signal is high.
READING PORT REGISTERS
To read the device data, the bus master must first send
____
the IS31SE5001 address with the R/W bit set to “0”,
followed by the command byte, which determines
which register is accessed. After a restart, the bus
master must then send the IS31SE5001 address with
____
the R/W bit set to “1”. Data from the register defined
by the command byte is then sent from the
IS31SE5001 to the master (Figure 5).
Figure 2 Interface timing
Figure 3 Bit transfer
Integrated Silicon Solution, Inc. – www.issi.com
Rev. B, 07/04/2013
5
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for IS31SE5001 electronic component. |
| Information | Total 11 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ IS31SE5001.PDF Datasheet ] | |
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