PDF IS45R83200D Data sheet ( Hoja de datos )

Número de pieza	IS45R83200D
Descripción	256-MBIT SYNCHRONOUS DRAM
Fabricantes	ISSI
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IS42R83200D, IS42R16160D IS45R83200D, IS45R16160D 32Meg x 8, 16Meg x16 256-MBIT SYNCHRONOUS DRAM MARCH 2010 FEATURES • Clock frequency: 133, 100 MHz • Fully synchronous; all signals referenced to a positive clock edge • Internal bank for hiding row access/precharge • Single Power supply: 2.5V + 0.2V • LVTTL interface • Programmable burst length – (1, 2, 4, 8, full page) • Programmable burst sequence: Sequential/Interleave • Auto Refresh (CBR) • Self Refresh • 8K refresh cycles every 16 ms (A2 grade) or 64 ms (commercial, industrial, A1 grade) • Random column address every clock cycle • Programmable CAS latency (2, 3 clocks) • Burst read/write and burst read/single write operations capability • Burst termination by burst stop and precharge command OPTIONS • Package: 54-pin TSOP-II (x8 and x16) 54-ball BGA (x16 only) • Operating Temperature Range: Commercial (0oC to +70oC) Industrial (-40oC to +85oC) Automotive Grade A1 (-40oC to +85oC) Automotive Grade A2 (-40oC to +105oC) OVERVIEW ISSI's 256Mb Synchronous DRAM achieves high-speed data transfer using pipeline architecture. All inputs and outputs signals refer to the rising edge of the clock input. The 256Mb SDRAM is organized as follows. IS42/45R83200D IS42/45R16160D 8M x 8 x 4 Banks 4M x16x4 Banks 54-pin TSOPII 54-pin TSOPII 54-ball BGA KEY TIMING PARAMETERS Parameter Clk Cycle Time CAS Latency = 3 CAS Latency = 2 Clk Frequency CAS Latency = 3 CAS Latency = 2 Access Time from Clock CAS Latency = 3 CAS Latency = 2 -75 7.5 10 133 100 5.4 6 Unit ns ns Mhz Mhz ns ns ADDRESS TABLE Parameter 32M x 8 Configuration 8M x 8 x 4 banks Refresh Count Com./Ind. A1 A2 8K/64ms 8K/64ms 8K/16ms Row Addresses A0-A12 Column Addresses A0-A9 Bank Address Pins BA0, BA1 Auto Precharge Pins A10/AP 16M x 16 4M x 16 x 4 banks 8K/64ms 8K/64ms 8K/16ms A0-A12 A0-A8 BA0, BA1 A10/AP Copyright © 2006 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time with- out notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. — www.issi.com Rev. A 03/02/2010 1 1 page IS42R83200D, IS42R16160D IS45R83200D, IS45R16160D PIN CONFIGURATION 54-ball fBGA for x16 (Top View) (8.00 mm x 13.00 mm Body, 0.8 mm Ball Pitch) package code: B 1 2 3 4 5 6 7 8 9 A B VSS DQ15 VSSQ C DQ14 DQ13 VDDQ D DQ12 DQ11 VSSQ E DQ10 DQ9 VDDQ F DQ8 NC VSS G DQMH CLK CKE H A12 A11 A9 J A8 A7 A6 VSS A5 A4 VDDQ DQ0 VDD VSSQ DQ2 DQ1 VDDQ DQ4 DQ3 VSSQ DQ6 DQ5 VDD DQML DQ7 CAS RAS WE BA0 BA1 CS A0 A1 A10 A3 A2 VDD PIN DESCRIPTIONS A0-A12 Row Address Input A0-A8 Column Address Input BA0, BA1 Bank Select Address DQ0 to DQ15 Data I/O CLK System Clock Input CKE Clock Enable CS Chip Select RAS Row Address Strobe Command CAS Column Address Strobe Command Integrated Silicon Solution, Inc. — www.issi.com Rev. A 03/02/2010 WE DQML DQMH Vdd Vss Vddq Vssq NC Write Enable x16 Lower Byte Input/Output Mask x16 Upper Byte Input/Output Mask Power Ground Power Supply for I/O Pin Ground for I/O Pin No Connection 5 5 Page IS42R83200D, IS42R16160D IS45R83200D, IS45R16160D FUNCTIONAL TRUTH TABLE Continued: Current State CS RAS CAS WE Address Command Read with auto Precharging H × × × × DESL L H H H x NOP L H H L × BST L H L H BA, CA, A10 READ/READA L H L L BA, CA, A10 WRIT/ WRITA L L H H BA, RA ACT L L H L BA, A10 PRE/PALL L L L H × REF/SELF L L L L OC, BA MRS Write with Auto Precharge H × × × × DESL L H H H × NOP L H H L × BST L H L H BA, CA, A10 READ/READA L H L L BA, CA, A10 WRIT/ WRITA L L H H BA, RA ACT L L H L BA, A10 PRE/PALL L L L H × REF/SELF L L L L OC, BA MRS Precharging H × × × × DESL L H H H × NOP L H H L × BST L H L H BA, CA, A10 READ/READA L H L L BA, CA, A10 WRIT/WRITA L L H H BA, RA ACT L L H L BA, A10 PRE/PALL L L L H × REF/SELF L L L L OC, BA MRS Row Activating H × × × × DESL L H H H × NOP L H H L × BST L H L H BA, CA, A10 READ/READA L H L L BA, CA, A10 WRIT/WRITA L L H H BA, RA ACT L L H L BA, A10 PRE/PALL L L L H × REF/SELF L L L L OC, BA MRS Action Continue burst to end, Precharge Continue burst to end, Precharge ILLEGAL ILLEGAL (11) ILLEGAL (11) ILLEGAL (3) ILLEGAL (11) ILLEGAL ILLEGAL Continue burst to end, Write recovering with auto precharge Continue burst to end, Write recovering with auto precharge ILLEGAL ILLEGAL(11) ILLEGAL (11) ILLEGAL (3,11) ILLEGAL (3,11) ILLEGAL ILLEGAL Nop, Enter idle after tRP Nop, Enter idle after tRP Nop, Enter idle after tRP ILLEGAL (3) ILLEGAL (3) ILLEGAL(3) Nop Enter idle after tRP ILLEGAL ILLEGAL Nop, Enter bank active after tRCD Nop, Enter bank active after tRCD Nop, Enter bank active after tRCD ILLEGAL (3) ILLEGAL (3) ILLEGAL (3,9) ILLEGAL (3) ILLEGAL ILLEGAL Note: H=Vih, L=Vil x= Vih or Vil, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code Integrated Silicon Solution, Inc. — www.issi.com Rev. A 03/02/2010 11 11 Page

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