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PDF 74HCT9046A Data sheet ( Hoja de datos )
| Número de pieza | 74HCT9046A | |
| Descripción | PLL | |
| Fabricantes | NXP Semiconductors | |
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74HCT9046A
PLL with band gap controlled VCO
Rev. 7 — 29 February 2016
Product data sheet
1. General description
The 74HCT9046A. This device features reduced input threshold levels to allow interfacing
to TTL logic levels. Inputs also include clamp diodes, this enables the use of current
limiting resistors to interface inputs to voltages in excess of VCC.
2. Features and benefits
Operation power supply voltage range from 4.5 V to 5.5 V
Low power consumption
Complies with JEDEC standard no. 7A
Inhibit control for ON/OFF keying and for low standby power consumption
center frequency up to 17 MHz (typical) at VCC = 5.5 V
Choice of two phase comparators:
PC1: EXCLUSIVE-OR
PC2: Edge-triggered JK flip-flop
No dead zone of PC2
Charge pump output on PC2, whose current is set by an external resistor Rbias
center frequency tolerance 10 %
Excellent Voltage Controlled Oscillator (VCO) linearity
Low frequency drift with supply voltage and temperature variations
On-chip band gap reference
Glitch free operation of VCO, even at very low frequencies
Zero voltage offset due to operational amplifier buffering
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
1 page  
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
7. Pinning information
7.1 Pinning
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Fig 5. Pin configuration
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7.2 Pin description
Table 2. Pin description
Symbol
Pin
GND
1
PC1_OUT/PCP_OUT
2
COMP_IN
3
VCO_OUT
4
INH 5
C1A 6
C1B 7
GND
8
VCO_IN
9
DEM_OUT
10
R1 11
R2 12
PC2_OUT
13
SIG_IN
14
RB 15
VCC 16
Description
ground (0 V) of phase comparators
phase comparator 1 output or phase comparator pulse output
comparator input
VCO output
inhibit input
capacitor C1 connection A
capacitor C1 connection B
ground (0 V) VCO
VCO input
demodulator output
resistor R1 connection
resistor R2 connection
phase comparator 2 output; current source adjustable with Rbias
signal input
bias resistor (Rbias) connection
supply voltage
74HCT9046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 29 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
5 of 44
5 Page 
NXP Semiconductors
74HCT9046A
PLL with band gap controlled VCO
When the frequency of SIG_IN is higher than that of COMP_IN, the source output driver is
held ‘ON’ for most of the input signal cycle time and for the remainder of the cycle time
both drivers are ‘OFF’ (3-state). If the SIG_IN frequency is lower than the COMP_IN
frequency, then it is the sink driver that is held ‘ON’ for most of the cycle. Subsequently the
voltage at the capacitor (C2) of the low-pass filter connected to PC2_OUT varies until the
signal and comparator inputs are equal in both phase and frequency. At this stable point
the voltage on C2 remains constant as the PC2 output is in 3-state and the VCO input at
pin 9 is a high-impedance. Also in this condition the signal at the phase comparator pulse
output (PCP_OUT) has a minimum output pulse width equal to the overlap time, so can
be used for indicating a locked condition.
Thus for PC2 no phase difference exists between SIG_IN and COMP_IN over the full
frequency range of the VCO. Moreover, the power dissipation due to the low-pass filter is
reduced because both output drivers are OFF for most of the signal input cycle. It should
be noted that the PLL lock range for this type of phase comparator is equal to the capture
range and is independent of the low-pass filter. With no signal present at SIG_IN the VCO
adjust, via PC2, to its lowest frequency.
By using current sources as charge pump output on PC2, the dead zone or backlash time
could be reduced to zero. Also, the pulse widening due to the parasitic output capacitance
plays no role here. This enables a linear transfer function, even in the vicinity of the zero
crossing. The differences between a voltage switch charge pump and a current switch
charge pump are shown in Figure 11.
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The pulse overlap of the up and down signals (typically 15 ns).
Fig 10. Timing diagram for PC2
PEG
74HCT9046A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7 — 29 February 2016
© NXP Semiconductors N.V. 2016. All rights reserved.
11 of 44
11 Page | ||
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| PDF Descargar | [ Datasheet 74HCT9046A.PDF ] | |
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